1. Field of the Invention
The present invention relates to a thin film transistor manufacturing method, thin film transistor and display device using the same.
2. Description of the Related Art
Recent years have paid attention being focused on a type of flat panel display, namely, a display device adapted to display video using organic EL (electro luminescence). This type of display device or organic EL display offers excellent characteristics including a wide view angle and low power consumption thanks to light emission of the organic light emitting element itself. Further, the organic EL display offers fast response to high-speed high-definition video signals. As a result, development efforts are underway for commercialization particularly in the video and other sectors.
Active matrix, a driving method of the organic EL display in which thin film transistors (TFTs) are used as driving elements, is superior to conventional passive matrix in terms of response time and resolution. Thus, this driving method is considered to be particularly suited to the organic EL display having the aforementioned characteristics. An active matrix organic EL display includes at least organic light-emitting elements (organic EL elements) having a light-emitting material and a drive panel having TFTs adapted to drive the organic light-emitting elements. This drive panel and a sealing panel are bonded together via an adhesive layer with organic EL elements sandwiched therebetween. Further, the active matrix organic EL display includes at least a switching transistor and drive transistor as TFTs making up the organic EL display. The switching transistor controls the pixel contrast. The drive transistor controls the light emission of the organic EL elements.
In such an organic EL display, controlling the gate voltage of the drive transistor regulates the current flowing into the organic EL element, thus controlling the display gray level. As a result, if the current flowing through the drive transistor differs significantly from one pixel to another, the light emission brightness of the display differs from one pixel to another. That is, the light emission of the organic EL element depends on the current flowing through the drive transistor. Suppression of the variation in the drive transistor current in an organic EL display is, therefore, extremely important to display an excellent image.
One factor behind the variation in TFT current is the variation in a “length L” of the TFT. Here, the term “length L of the TFT” refers to the source-to-drain distance of the TFT. That is, the finished source-to-drain distance of the channel etching stopper is the length L. Therefore, if this source-to-drain distance varies significantly across the finished surface, the ON current, which is one of the TFT characteristics, will vary accordingly.
Incidentally, the presence or absence of the variation in the length L of the TFT is known to depend upon the accuracy of forming a channel protective film. The channel protective film serves as an etching stopper during the formation of the source and drain. That is, the channel protective film is typically formed by first forming a resist pattern on top of a film formed with an insulating material and then masking and etching the resist pattern. In the etching process, however, if the etching rate varies, the source-to-drain distance in the TFT will accordingly vary.
A possible solution to the above problem would be to reduce the variation by means of self-aligned exposure and development using backside exposure from the gate electrode. However, this solution may not complement the variation in etching rate in the etching process. As a result, a problem remains to be solved: that is, the variation in etching rate will lead to the variation in length L of the TFT.
A possible solution to reduce the variation in etching shift during formation of the channel protective film, on the other hand, would be selective dry etching of the channel protective film formed on top of the silicon film by means of anisotropic dry etching. However, even anisotropic etching damages the resist pattern serving as a mask during etching of the channel protective film due to anisotropic ion collisions. As a result, the resist pattern itself may recede to reflect the variation in anisotropic dry etching. Therefore, even anisotropic dry etching fails to avoid the problem of the variation in finished source-to-drain distance.
On the other hand, it is difficult to achieve an approximately infinite selectivity to the silicon, for example, in the etching process using hydrogen fluoride solution. Instead, the [stopper etch rate/silicon damage rate] is at most 2 to 10. Therefore, if the channel protective film serving as a stopper is dry-etched through its entire thickness in one stroke, overetching is necessary which is appropriate for the variation in time resulting from etching through the entire film thickness. This results in more time occupied for overetching, possibly requiring the silicon film to be thicker. Further, if the channel protective film on the channel region is etched to the silicon for patterning with hydrogen fluoride solution, this solution may possibly find its way through pin holes of the silicon film, thus etching the gate insulating film. This may lead to reduced interlayer insulation capability of the gate insulating film.
Japanese Patent No. 2915397 discloses a hybrid layered structure of an insulating film serving as an etching stopper. This structure suppresses overhanging of the taper portion caused by etching with hydrogen fluoride solution, thus preventing transistor leakage. However, in the wet etching or isotropic etching of both layers to the silicon surface, the stopper insulating film being etched plays, in the middle of the wet etching process, the role of a mask for the remaining stopper insulating film, irrespective of the type of layered structure of the etching stopper. Therefore, dimensional variation resulting from isotropic etching variation is inevitable.
Japanese Patent Laid-Open No. Hei 9-298303 discloses a layered structure of the channel protective film. This structure suppresses damage to the gate insulating film caused by penetration of hydrofluoric acid through pin holes during dry etching. The structure also provides, for example, reduced etching damage to the silicon. However, during etching of the bottom layer of the layered structure after etching of the top layer thereof and removal of the resist, the top layer itself is used as a mask. As a result, the top layer's size at the completion of etching is transferred as the length L in an as-is manner. This leads to a variation in the length L because of etching variation of the top layer.
Japanese Patent Laid-Open No. Hei 6-188422 discloses a layered structure of the channel protective film. In the process following the formation of the same film (etching process of the n-plus layer), the top layer has a lower etching rate than the bottom layer so as to provide a reduced variation in remaining thickness of the channel protective film. This provides a reduced variation in transistor characteristics. However, the term “variation in transistor characteristics” as used herein is not related to the variation in the length L resulting from etching of the channel protective film itself. As a result, the problem caused by the variation in the length L remains to be solved.